Non-volatile memory with regional and inter-region wear leveling

ABSTRACT

A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to map the set of non-volatile memory cells into a plurality of regions, apply a first wear leveling scheme in a first region of the plurality of regions, and apply a second wear leveling scheme between the plurality of regions.

BACKGROUND

Semiconductor memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, and non-mobile computing devices. Semiconductor memory may comprise non-volatile memory or volatile memory. A non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power (e.g., a battery). Examples of non-volatile memory include flash memory (e.g., NAND-type and NOR-type flash memory), Electrically Erasable Programmable Read-Only Memory (EEPROM), resistive memory (e.g. ReRAM), ferroelectric memory (e.g., FeRAM), magnetoresistive memory (e.g., MRAM), and phase change memory (e.g., PRAM).

When a memory system is deployed in an electronic device, the memory system may program data, store data, read data and/or erase data. In some types of memory, cell characteristics of memory cells degrade with use so that memory cells tend to wear out after a certain amount of use (e.g. after being written a certain number of times). Different types of memories can have different wear-out characteristics and different memory access patterns can cause different patterns of wear. Wear leveling may be used to distribute wear across memory cells so that wear is not concentrated on particular memory cells, which could lead to early failure of such memory cells.

BRIEF DESCRIPTION OF THE DRAWINGS

Like-numbered elements refer to common components in the different figures.

FIG. 1 is a perspective view of a 3D stacked non-volatile memory device.

FIG. 2 is a functional block diagram of a memory device such as the 3D stacked non-volatile memory device 100 of FIG. 1.

FIG. 3 is a block diagram depicting one embodiment of a Controller.

FIGS. 4A-B illustrate an embodiment of a three-dimensional monolithic memory structure.

FIG. 5 illustrates two layers of an embodiment of a three-dimensional monolithic memory structure.

FIG. 6 illustrates an embodiment of a three-dimensional monolithic memory structure.

FIGS. 7A-I illustrate a start gap wear leveling scheme.

FIG. 8 illustrates a non-volatile memory with separate instances of a regional wear leveling operating independently in each region.

FIGS. 9A-B illustrates mapping of logical addresses to regions of a non-volatile memory.

FIGS. 10A-B illustrate a first mapping of groups of logical addresses to regions of a non-volatile memory in an inter-region wear leveling scheme.

FIGS. 11A-B illustrate a second mapping of groups of logical addresses to regions of a non-volatile memory in an inter-region wear leveling scheme.

FIGS. 12A-B illustrate a third mapping of groups of logical addresses to regions of a non-volatile memory in an inter-region wear leveling scheme.

FIGS. 13A-B illustrate a fourth mapping of groups of logical addresses to regions of a non-volatile memory in an inter-region wear leveling scheme.

FIGS. 14A-B illustrate a fifth mapping of groups of logical addresses to regions of a non-volatile memory in an inter-region wear leveling scheme.

FIG. 15 illustrates mapping of host logical addresses to groups according to expected access patterns.

FIG. 16 illustrates mapping of regions according to expected endurance limits.

FIGS. 17A-B illustrate a first mapping of logical groups to regions according to expected access patterns and endurance limits.

FIG. 18 illustrates an inter-region wear leveling scheme according to regional wear data.

FIG. 19 illustrates recording regional wear data and recording group write data.

FIG. 20 shows a method of operating wear leveling schemes.

FIG. 21 illustrates an example of hardware for implementing regional and inter-region wear leveling.

DETAILED DESCRIPTION

In a non-volatile memory system, memory cells may be mapped into regions with regional wear leveling applied individually to regions. Regional wear leveling may be relatively simple so that operation of regional wear leveling may be performed without using significant resources and without significantly impacting other memory operations. For example, a deterministic wear leveling scheme (also referred to as a “mathematical” wear leveling scheme) may remap host data to physical locations in memory according to a predetermined algorithm, such as by offsetting logical to physical address mapping according to an offset that is incremented with use. A deterministic scheme does not account for changing characteristics of memory cells and proceeds blindly moving data according (e.g. incrementing locations).

In addition to regional wear leveling, inter-region wear leveling may be applied to level wear between regions and avoid concentration of wear in a particular region or regions. Inter-region wear leveling may be a simple wear leveling scheme such as a deterministic wear leveling scheme. Alternatively, inter-region wear leveling may be based on wear experienced by regions. Wear may be measured and indicators of wear may be maintained for each region (e.g. an indicator of the number of writes experienced by each region, an increase in bit errors after a write verify, media retention behavior). Logical address mapping may be exchanged between a region that has experienced relatively high wear and a region that has experienced relatively low wear so that frequently written data is mapped to memory cells with lower wear and infrequently written data is mapped to cells with higher wear.

In some cases, a host access characteristics or desires may be provided to the device, determined by the device, or assumed by the device. For example, the host may identify a boot partition or frequently demanded data. In another example, the device may recognize the read or write access rate for a set of logical addresses. A device may also recognize or assume another host pattern and make logical address layout decisions to optimize group usage or information regarding expected access frequency (e.g. write frequency) for some logical addresses. Such information may be used to map host logical addresses into groups according to expected access frequency. These groups may then be individually mapped to regions. In some cases, characteristics of different physical areas of a memory array may be known. For example, certain areas may have different media properties such as low expected endurance because of physical characteristics of memory cells while other areas may have high expected endurance, e.g. memory cells at different physical levels above a substrate in a 3-D memory array may have different media properties including endurance characteristics. Areas of high expected endurance (with high expected endurance limit) may be mapped into particular regions while areas of low expected endurance (with low expected endurance limit) may be mapped to other regions and logical groups may be allocated to these regions accordingly. For example, a group containing frequently written data may be allocated to a high endurance region while a group containing infrequently written data may be allocated to a low endurance region. Other media properties than endurance may be used for these placement decisions such as media latency, media bit error accumulation rate, placement for minimized access conflicts, or device temperature gradient dispersion across multiple die or packages.

FIGS. 1-3 describe one example of a memory system that can be used to implement the technology proposed herein. FIG. 1 is a perspective view of a three-dimensional (3D) stacked non-volatile memory device. The memory device 100 includes a substrate 101. On and above the substrate are example blocks of memory cells, including BLK0 and BLK1, formed of memory cells (non-volatile storage elements). Also on substrate 101 is peripheral area 104 with support circuits for use by the blocks. Substrate 101 can also carry circuits under the blocks, along with one or more lower metal layers which are patterned in conductive paths to carry signals of the circuits. The blocks are formed in an intermediate region 102 of the memory device. In an upper region 103 of the memory device, one or more upper metal layers are patterned in conductive paths to carry signals of the circuits. Each block of memory cells comprises a stacked area of memory cells, where alternating levels of the stack represent word lines. While two blocks are depicted as an example, additional blocks can be used, extending in the x- and/or y-directions.

In one example implementation, the length of the plane in the x-direction, represents a direction in which signal paths for word lines extend (a word line or SGD line direction), and the width of the plane in the y-direction, represents a direction in which signal paths for bit lines extend (a bit line direction). The z-direction represents a height of the memory device.

FIG. 2 is a functional block diagram of an example memory device such as the 3D stacked non-volatile memory device 100 of FIG. 1. The components depicted in FIG. 2 are electrical circuits. Memory device 100 includes one or more memory die 108. Each memory die 108 includes a three-dimensional memory structure 126 of memory cells (such as, for example, a 3D array of memory cells), control circuitry 110, and read/write circuits 128. In other embodiments, a two-dimensional array of memory cells can be used. Memory structure 126 is addressable by word lines via a decoder 124 (row decoder) and by bit lines via a column decoder 132. The read/write circuits 128 include multiple sense blocks 150 including SB1, SB2, . . . , SBp (sensing circuitry) and allow a page of memory cells to be read or programmed in parallel. In some systems, a Controller 122 is included in the same memory device, such as memory device 100 (e.g., a removable storage card) as the one or more memory die 108. However, in other systems, the Controller can be separated from the memory die 108. In some embodiments, the Controller will be on a different die than the memory die. In some embodiments, one Controller 122 will communicate with multiple memory die 108. In other embodiments, each memory die 108 has its own Controller. Commands and data are transferred between the host 140 and Controller 122 via a data bus 120, and between Controller 122 and the one or more memory die 108 via lines 118. In one embodiment, memory die 108 includes a set of input and/or output (I/O) pins that connect to lines 118.

Memory structure 126 may comprise one or more arrays of memory cells including a 3D array. The memory structure may comprise a monolithic three-dimensional memory structure in which multiple memory levels are formed above (and not in) a single substrate, such as a wafer, with no intervening substrates. The memory structure may comprise any type of non-volatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate. The memory structure may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate.

Control circuitry 110 cooperates with the read/write circuits 128 to perform memory operations (e.g., erase, program, read, and others) on memory structure 126, and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. The state machine 112 provides chip-level control of memory operations. Temperature detection circuit 113 is configured to detect temperature, and can be any suitable temperature detection circuit known in the art. In one embodiment, state machine 112 is programmable by the software. In other embodiments, state machine 112 does not use software and is completely implemented in hardware (e.g., electrical circuits). In one embodiment, control circuitry 110 includes registers, ROM fuses and other storage devices for storing default values such as base voltages and other parameters.

The on-chip address decoder 114 provides an address interface between addresses used by host 140 or Controller 122 to the hardware address used by the decoders 124 and 132. Power control module 116 controls the power and voltages supplied to the word lines and bit lines during memory operations. It can include drivers for word line layers (discussed below) in a 3D configuration, select transistors (e.g., SGS and SGD transistors, described below) and source lines. Power control module 116 may include charge pumps for creating voltages. The sense blocks include bit line drivers.

Any one or any combination of control circuitry 110, state machine 112, decoders 114/124/132, temperature detection circuit 113, power control module 116, sense blocks 150, read/write circuits 128, and Controller 122 can be considered one or more control circuits (or a managing circuit) that performs the functions described herein.

The (on-chip or off-chip) Controller 122 (which in one embodiment is an electrical circuit) may comprise one or more processors 122 c, ROM 122 a, RAM 122 b, Memory interface 122 d and Host Interface 122 e, all of which are interconnected. One or more processors 122C is one example of a control circuit. Other embodiments can use state machines or other custom circuits designed to perform one or more functions. The storage devices (ROM 122 a, RAM 122 b) comprises code such as a set of instructions, and the processor 122 c is operable to execute the set of instructions to provide the functionality described herein. Alternatively, or additionally, processor 122 c can access code from a storage device in the memory structure, such as a reserved area of memory cells connected to one or more word lines. Memory interface 122 d, in communication with ROM 122 a, RAM 122 b and processor 122 c, is an electrical circuit that provides an electrical interface between Controller 122 and memory die 108. For example, memory interface 122 d can change the format or timing of signals, provide a buffer, isolate from surges, latch I/O, etc. Processor 122C can issue commands to control circuitry 110 (or any other component of memory die 108) via Memory interface 122 d. Host Interface 122 e in communication with ROM 122 a, RAM 122 b and processor 122 c, is an electrical circuit that provides an electrical interface between Controller 122 and host 140. For example, Host Interface 122 e can change the format or timing of signals, provide a buffer, isolate from surges, latch I/O, etc. Commands and data from host 140 are received by Controller 122 via Host Interface 122 e. Data sent to host 140 are transmitted via Host Interface 122 e.

Multiple memory elements in memory structure 126 may be configured so that they are connected in series or so that each element is individually accessible. By way of non-limiting example, flash memory devices in a NAND configuration (NAND flash memory) typically contain memory elements connected in series. Alternatively, memory elements may be configured so that each element is individually accessible.

The memory cells may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in non-regular or non-orthogonal configurations, or in structures not considered arrays.

A three-dimensional memory array is arranged so that memory cells occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y and z directions, where the z direction is substantially perpendicular and the x and y directions are substantially parallel to the major surface of the substrate).

As a non-limiting example, a three-dimensional memory structure may be vertically arranged as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in they direction) with each column having multiple memory cells. The vertical columns may be arranged in a two-dimensional configuration, e.g., in an x-y plane, resulting in a three-dimensional arrangement of memory cells, with memory cells on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three-dimensional memory array.

A person of ordinary skill in the art will recognize that the technology described herein is not limited to a single specific memory structure, but covers many relevant memory structures within the spirit and scope of the technology as described herein and as understood by one of ordinary skill in the art.

FIG. 3 is a block diagram of an example memory system 100, depicting more details of Controller 122. In one embodiment, the system of FIG. 3 is a solid-state drive (SSD). As used herein, a flash memory Controller is a device that manages data stored on non-volatile memory and communicates with a host, such as a computer or electronic device. A non-volatile memory Controller can have various functionality in addition to the specific functionality described herein. For example, the non-volatile memory Controller can format the non-volatile memory to ensure the memory is operating properly, map out bad non-volatile memory cells, and allocate spare memory cells to be substituted for future failed memory cells. Some part of the spare memory cells can be used to hold firmware to operate the non-volatile memory Controller and implement other features. In operation, when a host needs to read data from or write data to the non-volatile memory, it will communicate with the non-volatile memory Controller. If the host provides a logical address to which data is to be read/written, the non-volatile memory Controller can convert the logical address received from the host to a physical address in the non-volatile memory. (Alternatively, the host can provide the physical address). The non-volatile memory Controller can also perform various memory management functions, such as, but not limited to, wear leveling (distributing writes to avoid wearing out specific blocks of memory that would otherwise be repeatedly written to) and garbage collection (after a block is full in a block-erased memory, moving only the valid pages of data to a new block, so the full block can be erased and reused).

The communication interface between Controller 122 and non-volatile memory die 108 may be any suitable interface, such as Open NAND flash interface (ONFI), Toggle Mode 200, 400, or 800. In one embodiment, memory system 100 may be a card based system, such as a secure digital (SD) or a micro secure digital (micro-SD) card. In an alternate embodiment, memory system 100 may be part of an embedded memory system. For example, the non-volatile memory may be embedded within the host, such as in the form of a solid-state disk (SSD) drive installed in a personal computer or as a non-volatile dual in-line memory module (NVDIMM) in a host system.

In some embodiments, memory system 100 includes a single channel between Controller 122 and non-volatile memory die 108, the subject matter described herein is not limited to having a single memory channel. For example, in some memory system architectures, 2, 4, 8 or more channels may exist between the Controller and the memory die, depending on Controller capabilities. In any of the embodiments described herein, more than a single channel may exist between the Controller and the memory die, even if a single channel is shown in the drawings.

As depicted in FIG. 3, Controller 122 includes a front-end module 208 that interfaces with a host, a back-end module 210 that interfaces with the one or more non-volatile memory die 108, and various other modules that perform functions which will now be described in detail.

The components of Controller 122 depicted in FIG. 3 may take the form of a packaged functional hardware unit (e.g., an electrical circuit) designed for use with other components, a portion of a program code (e.g., software or firmware) executable by a (micro)processor or processing circuitry (or one or more processors) that usually performs a particular function of related functions, or a self-contained hardware or software component that interfaces with a larger system, for example. For example, each module may include an application specific integrated circuit (ASIC), a Field Programmable Gate Array (FPGA), a circuit, a digital logic circuit, an analog circuit, a combination of discrete circuits, gates, or any other type of hardware or combination thereof. Alternatively, or in addition, each module may include or comprise software stored in a processor readable device (e.g., memory) to program one or more processors for Controller 122 to perform the functions described herein. The architecture depicted in FIG. 3 is one example implementation that may (or may not) use the components of Controller 122 depicted in FIG. 2 (i.e. RAM, ROM, processor, interface).

Referring again to modules of the Controller 122, a buffer manager/bus Controller 214 manages buffers in random access memory (RAM) 216 and controls the internal bus arbitration of Controller 122. A read only memory (ROM) 218 stores system boot code. Although illustrated in FIG. 3 as located separately from the Controller 122, in other embodiments one or both of the RAM 216 and ROM 218 may be located within the Controller. In yet other embodiments, portions of RAM and ROM may be located both within the Controller 122 and outside the Controller. Further, in some implementations, the Controller 122, RAM 216, and ROM 218 may be located on separate semiconductor die.

Front-end module 208 includes a host interface 220 and a physical layer interface 222 (PHY) that provide the electrical interface with the host or next level storage Controller. The choice of the type of host interface 220 can depend on the type of memory being used. Examples of host interfaces 220 include, but are not limited to, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe. The host interface 220 may be a communication interface that facilitates transfer for data, control signals, and timing signals.

Back-end module 210 includes an error correction Controller (ECC) engine, ECC engine 224, that encodes the data bytes received from the host, and decodes and error corrects the data bytes read from the non-volatile memory. A command sequencer 226 generates command sequences, such as program and erase command sequences, to be transmitted to non-volatile memory die 108. A RAID (Redundant Array of Independent Dies) module 228 manages generation of RAID parity and recovery of failed data. The RAID parity may be used as an additional level of integrity protection for the data being written into the memory system 100. In some cases, the RAID module 228 may be a part of the ECC engine 224. Together, ECC engine 224 and RAID module 228 may be considered to form a combined redundancy encoder 234. A memory interface 230 provides the command sequences to non-volatile memory die 108 and receives status information from non-volatile memory die 108. In one embodiment, memory interface 230 may be a double data rate (DDR) interface, such as a Toggle Mode 200, 400, or 800 interface. A non-volatile control layer 232 controls the overall operation of back-end module 210.

Additional components of memory system 100 illustrated in FIG. 3 include media management layer 238, which performs wear leveling of memory cells of non-volatile memory die 108. Memory system 100 also includes other discrete components 240, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may interface with Controller 122. In alternative embodiments, one or more of the physical layer interface 222, RAID module 228, media management layer 238 and buffer management/bus Controller 214 are optional components that are not necessary in the Controller 122.

The Media Management Layer (MML) 238 (also referred to as a Flash Translation Layer, or FTL, in the case where non-volatile memory is flash) may be integrated as part of the non-volatile management that may handle errors and interfacing with the host. MML may be a module in memory management. In particular, the MML 238 may include an algorithm in the memory device firmware which translates writes from the host into writes to the non-volatile memory 126 of memory die 108. The MML 238 may be needed because: 1) the non-volatile memory may have limited endurance, retention, or be susceptible to disturbances from other media activites; 2) the non-volatile memory 126 may only be written in multiples of pages; and/or 3) the non-volatile memory 126 may not be written unless it is erased as a block (i.e. a block may be considered to be a minimum unit of erase). The MML 238 understands these potential limitations of the non-volatile memory 126 which may not be visible to the host. Accordingly, the MML 238 attempts to translate the writes from host into writes into the non-volatile memory 126.

Controller 122 may interface with one or more memory die 108. In in one embodiment, Controller 122 and multiple memory dies (together comprising memory system 100) implement a solid-state drive (SSD), which can emulate, replace or be used instead of a hard disk drive inside a host, as a NAS device, etc. Additionally, the SSD need not be made to work as a hard drive.

FIG. 4A depicts one embodiment of a portion of a monolithic three-dimensional memory array 416 that includes a first memory level 412 positioned below a second memory level 410. Memory array 416 is one example of an implementation for three-dimensional memory structure 126 in FIG. 2. As depicted, the local bit lines LBL11-LBL33 are arranged in a first direction (i.e., a vertical direction) and the word lines WL10-WL23 are arranged in a second direction perpendicular to the first direction. This arrangement of vertical bit lines in a monolithic three-dimensional memory array is one embodiment of a vertical bit line memory array. As depicted, disposed between the intersection of each local bit line and each word line is a particular memory cell (e.g., memory cell M111 is disposed between local bit line LBL11 and word line WL10). In one example, the particular memory cell may include a floating gate device or a charge trap device (e.g., using a silicon nitride material). In another example, the particular memory cell may include a reversible resistance-switching material, a metal oxide, a phase change material, or a ReRAM material. The global bit lines GBL1-GBL3 are arranged in a third direction that is perpendicular to both the first direction and the second direction. A set of bit line select devices (e.g., Q11-Q31) may be used to select a set of local bit lines (e.g., LBL11-LBL31). As depicted, bit line select devices Q11-Q31 are used to select the local bit lines LBL11-LBL31 and to connect the local bit lines LBL11-LBL31 to the global bit lines GBL1-GBL3 using row select line SG1. Similarly, bit line select devices Q12-Q32 are used to selectively connect the local bit lines LBL12-LBL32 to the global bit lines GBL1-GBL3 using row select line SG2 and bit line select devices Q13-Q33 are used to selectively connect the local bit lines LBL13-LBL33 to the global bit lines GBL1-GBL3 using row select line SG3.

In one embodiment, a vertical bit line memory array, such as memory array 416, includes a greater number of memory cells along the word lines as compared with the number of memory cells along the vertical bit lines (e.g., the number of memory cells along a word line may be more than 10 times the number of memory cells along a bit line). In one example, the number of memory cells along each bit line may be 16 or 32, while the number of memory cells along each word line may be 2048 or more than 4096. In another embodiment, the memory cells accessed in parallel may be more granular such as 1, 64, or 128.

FIG. 4B depicts one embodiment of a portion of a monolithic three-dimensional memory array that includes vertical strips of a non-volatile memory material. The physical structure depicted in FIG. 4B may comprise one implementation for a portion of the monolithic three-dimensional memory array depicted in FIG. 4A. The vertical strips of non-volatile memory material may be formed in a direction that is perpendicular to a substrate (e.g., in the Z direction). A vertical strip of the non-volatile memory material 414 may include, for example, a vertical oxide layer, a vertical metal oxide layer (e.g., nickel oxide or hafnium oxide), a vertical layer of phase change material, or a vertical charge trapping layer (e.g., a layer of silicon nitride). The vertical strip of material may comprise a single continuous layer of material that may be used by a plurality of memory cells or devices. In one example, portions of the vertical strip of the non-volatile memory material 414 may comprise a part of a first memory cell associated with the cross section between WL12 and LBL13 and a part of a second memory cell associated with the cross section between WL22 and LBL13. In some cases, a vertical bit line, such as LBL13, may comprise a vertical structure (e.g., a rectangular prism, a cylinder, or a pillar) and the non-volatile material may completely or partially surround the vertical structure (e.g., a conformal layer of phase change material surrounding the sides of the vertical structure in phase change memory cells). As depicted, each of the vertical bit lines may be connected to one of a set of global bit lines via a select transistor. The select transistor may comprise a MOS device (e.g., an NMOS device) or a vertical thin-film transistor (TFT).

FIG. 5 depicts one embodiment of a portion of a monolithic three-dimensional memory array 201 that includes a second memory level 520 positioned above a first memory level 518. Memory array 201 is one example of an implementation for non-volatile memory die 108. The bit lines 506 and 510 are arranged in a first direction and the word lines 508 are arranged in a second direction perpendicular to the first direction. As depicted, the upper conductors of first memory level 518 may be used as the lower conductors of the second memory level 520 that is positioned above the first memory level. In a memory array with additional layers of memory cells, there would be corresponding additional layers of bit lines and word lines.

As depicted in FIG. 5, memory array 201 includes a plurality of memory cells 200. The memory cells 200 may include re-writeable memory cells. The memory cells 200 may include non-volatile memory cells or volatile memory cells. With respect to first memory level 518, a first portion of memory cells 200 are between and connect to bit lines 206 and word lines 508. With respect to second memory level 520, a second portion of memory cells 200 are between and connect to bit lines 510 and word lines 508. In one embodiment, each memory cell includes a steering element (e.g., a diode) and a memory element (i.e., a state change element). In one example, the diodes of the first memory level 518 may be upward pointing diodes as indicated by arrow A₁ (e.g., with p regions at the bottom of the diodes), while the diodes of the second memory level 520 may be downward pointing diodes as indicated by arrow A₂ (e.g., with n regions at the bottom of the diodes), or vice versa. In another embodiment, each memory cell includes a state change element and does not include a steering element. The absence of a diode (or other steering element) from a memory cell may reduce the process complexity and costs associated with manufacturing a memory array.

In one embodiment, the memory cells 200 of FIG. 5 may comprise re-writable non-volatile memory cells including a reversible resistance-switching element. A reversible resistance-switching element may include a reversible resistivity-switching material having a resistivity that may be reversibly switched between two or more states. In one embodiment, the reversible resistance-switching material may include a metal oxide (e.g., a binary metal oxide). The metal oxide may include nickel oxide or hafnium oxide. In another embodiment, the reversible resistance-switching material may include a phase change material. The phase change material may include a chalcogenide material. In some cases, the re-writeable non-volatile memory cells may comprise resistive RAM (ReRAM) devices.

In another embodiment, the memory cells 200 of FIG. 5 may include conductive bridge memory elements. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge memory element may be used as a state change element based on the physical relocation of ions within a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of the solid electrolyte between the two electrodes. As temperature increases, the mobility of the ions also increases causing the programming threshold for the conductive bridge memory cell to decrease. Thus, the conductive bridge memory element may have a wide range of programming thresholds over temperature.

Different types of non-volatile memory may have very different media properties, including endurance characteristics and may have different likely failure modes. For example, block-erasable memories may use logical-to-physical mapping to accommodate writing the same data to different locations (e.g. when data is updated it may be written in a new block). A wear leveling scheme may remap data from a heavily worn block in such a memory and write-erase cycles may be counted on a block-by-block basis. Certain types of non-volatile memory do not require an erase between writes (previous data may be overwritten) and may be considered write-in-place memories. Some write-in-place memories are proposed as candidates to replace DRAM main memory in some processing systems because of their high read and write speeds and may be referred to as “storage class memory” or SCM. Unlike DRAM, such memories retain data when power is lost and may also be referred to as “persistent memory.” ReRAM, MRAM, and Phase Change Memory (PCM) may be considered persistent memory examples and may be considered as SCM. Some forms of SCM may have relatively low endurance compared to DRAM. While overwriting old data with corresponding replacement data allows fast writing and simplifies memory management, if particular data is frequently updated, a corresponding physical area may become worn rapidly. Thus, wear leveling for write-in-place memories poses particular challenges. While aspects of the present technology are described with respect to write-in-place memories, it will be understood that the present technology is applicable to any suitable memory and is not limited to write-in-place.

Referring to FIG. 5, in one embodiment of a read operation, the data stored in one of the plurality of memory cells 200 may be read by biasing one of the word lines (i.e., the selected word line) to a selected word line voltage in read mode (e.g., 0V). A read circuit may then be used to bias a selected bit line connected to the selected memory cell to the selected bit line voltage in read mode (e.g., 1.0V). In some cases, in order to avoid sensing leakage current from the many unselected word lines to the selected bit line, the unselected word lines may be biased to the same voltage as the selected bit lines (e.g., 1.0V). To avoid leakage current from the selected word line to the unselected bit lines, the unselected bit lines may be biased to the same voltage as the selected word line (e.g., 0V); however, biasing the unselected word lines to the same voltage as the selected bit lines and biasing the unselected bit lines to the same voltage as the selected word line may place a substantial voltage stress across the unselected memory cells driven by both the unselected word lines and the unselected bit lines.

In an alternative read biasing scheme, both the unselected word lines and the unselected bit lines may be biased to an intermediate voltage that is between the selected word line voltage and the selected bit line voltage. Applying the same voltage to both the unselected word lines and the unselected bit lines may reduce the voltage stress across the unselected memory cells driven by both the unselected word lines and the unselected bit lines; however, the reduced voltage stress comes at the expense of increased leakage currents associated with the selected word line and the selected bit line. Before the selected word line voltage has been applied to the selected word line, the selected bit line voltage may be applied to the selected bit line, and a read circuit may then sense an auto zero amount of current through the selected memory bit line which is subtracted from the bit line current in a second current sensing when the selected word line voltage is applied to the selected word line. The leakage current may be subtracted out by using the auto zero current sensing.

Referring to FIG. 5, in one embodiment of a write operation, the reversible resistance-switching material may be in an initial high-resistivity state that is switchable to a low-resistivity state upon application of a first voltage and/or current. Application of a second voltage and/or current may return the reversible resistance-switching material back to the high-resistivity state. Alternatively, the reversible resistance-switching material may be in an initial low-resistance state that is reversibly switchable to a high-resistance state upon application of the appropriate voltage(s) and/or current(s). When used in a memory cell, one resistance state may represent a binary data “0” while another resistance state may represent a binary data “1.” In some cases, a memory cell may be considered to comprise more than two data/resistance states (i.e., a multi-level memory cell). In some cases, a write operation may be similar to a read operation except with a larger voltage range placed across the selected memory cells.

The process of switching the resistance of a reversible resistance-switching element from a high-resistivity state to a low-resistivity state may be referred to as SETTING the reversible resistance-switching element. The process of switching the resistance from the low-resistivity state to the high-resistivity state may be referred to as RESETTING the reversible resistance-switching element. The high-resistivity state may be associated with binary data “1” and the low-resistivity state may be associated with binary data “0.” In other embodiments, SETTING and RESETTING operations and/or the data encoding may be reversed. For example, the high-resistivity state may be associated with binary data “0” and the low-resistivity state may be associated with binary data “1.” In some embodiments, a higher than normal programming voltage may be required the first time a reversible resistance-switching element is SET into the low-resistivity state as the reversible resistance-switching element may have been placed into a resistance state that is higher than the high-resistivity state when fabricated. The term “FORMING” may refer to the setting of a reversible resistance-switching element into a low-resistivity state for the first time after fabrication or the resetting of a reversible resistance-switching element into a high-resistivity state for the first time after fabrication. In some cases, after a FORMING operation or a memory cell preconditioning operation has been performed, the reversible resistance-switching element may be RESET to the high-resistivity state and then SET again to the low-resistivity state.

FIG. 6 is a perspective view of a portion of another embodiment of a three-dimensional memory structure 126, which includes a plurality memory cells. For example, FIG. 6 shows a portion of one block of a block-erasable memory and is one example of an implementation for non-volatile memory die 108. The structure depicted includes a set of bit lines BL positioned above a stack of alternating dielectric layers and conductive layers. For example, purposes, one of the dielectric layers is marked as D and one of the conductive layers (also called word line layers) is marked as W. The number of alternating dielectric layers and conductive layers can vary based on specific implementation requirements. One set of embodiments includes between 108-216 alternating dielectric layers and conductive layers, for example, 96 data word line layers, 8 select layers, 4 dummy word line layers and 108 dielectric layers. More or less than 108-216 layers can also be used. As will be explained below, the alternating dielectric layers and conductive layers are divided into four “fingers” by local interconnects LI. FIG. 6 only shows two fingers and two local interconnects LI. Below and the alternating dielectric layers and word line layers is a source line layer SL. Memory holes are formed in the stack of alternating dielectric layers and conductive layers. For example, one of the memory holes is marked as MH. Note that in FIG. 6, the dielectric layers are depicted as see-through so that the reader can see the memory holes positioned in the stack of alternating dielectric layers and conductive layers. In one embodiment, NAND strings are formed by filling the memory hole with materials including a charge-trapping layer to create a vertical column of memory cells. Each memory cell can store one or more bits of data.

Although the example memory system of FIG. 6 is a three-dimensional memory structure that includes vertical NAND strings with charge-trapping material, other (2D and 3D) memory structures can also be used with the technology described herein. For example, floating gate memories (e.g., NAND-type and NOR-type flash memory, ReRAM memories, magnetoresistive memory (e.g., MRAM), and phase change memory (e.g., PCRAM) can also be used.

One example of a ReRAM memory includes reversible resistance-switching elements arranged in cross point arrays accessed by X lines and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cells may include conductive bridge memory elements. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge memory element may be used as a state change element based on the physical relocation of ions within a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of the solid electrolyte between the two electrodes. As temperature increases, the mobility of the ions also increases causing the programming threshold for the conductive bridge memory cell to decrease. Thus, the conductive bridge memory element may have a wide range of programming thresholds over temperature.

Magnetoresistive memory (MRAM) stores data by magnetic storage elements. The elements are formed from two ferromagnetic plates, each of which can hold a magnetization, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a particular polarity; the other plate's magnetization can be changed to match that of an external field to store memory. This configuration is known as a spin valve and is the simplest structure for an MRAM bit. A memory device is built from a grid of such memory cells. In one embodiment for programming a non-volatile storage system, each memory cell lies between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below the cell. When current is passed through them, an induced magnetic field is created.

Phase change memory (PCM, or PCRAM) exploits the unique behavior of chalcogenide glass. One embodiment uses a GeTe—Sb2Te3 super lattice to achieve non-thermal phase changes by simply changing the co-ordination state of the Germanium atoms with a laser pulse (or light pulse from another source). Therefore, the doses of programming are laser pulses. The memory cells can be inhibited by blocking the memory cells from receiving the light. Note that the use of “pulse” in this document does not require a square pulse, but includes a (continuous or non-continuous) vibration or burst of sound, current, voltage light, or other wave. PCM may also be operated and controlled by electrical currents for heating and cooling rather than lasers.

While specific examples of memory cells and memory array design are described above, it will be understood that the presently described technology is not limited to a particular type of memory cell, or to a particular array design.

Different types of non-volatile memory have different requirements. Some memory devices require an erase operation to reuse memory cells that contain obsolete data. For example, flash memory cells that are written are generally erased before they are used to store new data (i.e. overwriting existing data with new data is not commonly done in flash memory). In general, the unit of erase (referred to as an “erase block” or “block”) is larger than the unit of programming (referred to as a “page”) so that when a page of data is to be updated, it is not generally practical to erase the physical page containing a previous copy of the data. In such systems, updated data may be written to a different physical location and the previous copy becomes obsolete. Logical addresses provided by the host may be mapped to physical addresses in a memory array using a mapping scheme that allows incoming data to be written to different memory cells that are already erased, often in a different block. Such mapping schemes may become quite complex as a memory fills with data and updated data is written to available spaces. Maintaining such a mapping scheme may require significant resources.

Some non-volatile memories allow memory cells to be reprogrammed without an erase operation (i.e. allow data to be overwritten). In such non-volatile memories, it is possible to write updated data at the same location as a previous copy of the data. Such memories may be referred to as “program-in-place” memories. Such memories allow host data to be mapped to physical locations in a non-volatile memory array in a simple manner. For example, each host address may map to a corresponding physical address in a one-to-one mapping scheme so that host addresses correspond to physical addresses in a static mapping. This may be considered a physical addressing scheme.

Some non-volatile memories have characteristics that allow them to be used in applications traditionally served by volatile memories, e.g. DRAM and SRAM. Such memories may be referred to as “storage class memory” and include program-in-place memories. Phase Change Memory (PCM) and ReRAM may be considered as examples of storage class memory. Such memories may be used to replace a traditional dual in-line memory module (DIMM) that contains DRAM with non-volatile DIMM (NVDIMM).

In some non-volatile memories, memory cells tend to wear out with use. Different types of memory generally have different media properties including endurance characteristics (different expected endurance limits) so that some types of memory wear out rapidly while others may endure a lot of wear without significant degradation. Some non-volatile memory systems use wear leveling to distribute wear across a memory and avoid concentration of wear in particular areas. In NAND flash memory, wear leveling schemes may be applied as part of a logical to physical mapping scheme, which is often used in such memories. In other memories, such as program-in-place memories, including PCM and ReRAM, a full logical to physical mapping scheme may not be necessary and may not be desirable because of the resources needed for such a scheme. However, some program-in-place memories have poor endurance characteristics (e.g. low expected endurance limit) so that wear leveling may be particularly important.

Certain examples presented here refer to wear leveling schemes that do not require maintaining a full logical to physical map for a memory array. While such schemes may be convenient for program-in-place memories including PCM and ReRAM, it will be understood that they may be applied to any type of memory.

FIGS. 7A-I show a simple example of a deterministic wear leveling scheme applied to a region of a non-volatile memory that includes 5 physical pages. Logical pages A-D are mapped to physical pages 0-4 (physical page numbers in the left column) in a cycle, with a gap rotating through the memory as logical pages are displaced. It will be understood that non-volatile memories, or memory regions, generally contain more than 5 physical pages to store more than 4 logical pages and that the present example is simplified for illustrative purposes.

FIG. 7A illustrates a first mapping of logical pages to physical pages in which logical page A is mapped to physical page 1, logical page B is mapped to logical page 1, logical page C is mapped to logical page 2, and logical page D is mapped to physical page 3. No logical page is mapped to physical page 4 so that physical page 4 is unwritten in this example and forms a gap in the mapping scheme.

FIG. 7B illustrates a second mapping of logical pages to physical pages in which logical page D and the gap are swapped. Thus, logical page D is mapped to physical page 4 (position incremented by one place) and physical page 3 is unwritten so that it forms a gap in the mapping scheme. The mapping of logical pages A-C to physical pages 0-2 respectively remains as before. Remapping may be performed by copying logical page D from physical page 3 to physical page 4 and updating a pointer that indicates the location of the gap from physical page 4 to physical page 3. In memories that require erasing before memory cells are written again physical page 3 may be erased.

Remapping from the first mapping of FIG. 7A to the second mapping of FIG. 7B may be performed in response to a triggering event such as an amount of elapsed time, or an amount of wear indicated by a number of read and/or write and/or erase operations performed on the memory, or some other event. For example, after a hundred writes to physical pages 0-4 collectively, remapping may be performed. In this way, individual counts are not necessary for each physical page and there is relatively little overhead (particularly for larger numbers of physical pages in a memory, or region of a memory). The number of writes that triggers a remapping may be selected according to the expected endurance of the memory cells, the number of physical pages in a group, and/or other factors. In some cases, instead of recording all writes to a region, some sampling may be performed and used to estimate a total number of writes to the region. This may reduce overhead associated with maintaining counts.

FIG. 7C illustrates a subsequent mapping of logical pages to physical pages in which logical page C is swapped with the gap. Logical page C is mapped to physical page 3 and the gap is mapped to physical page 2 (e.g. by updating a gap pointer). Mapping of other logical pages to physical pages remains as in FIG. 7B.

FIG. 7D illustrates a subsequent mapping of logical pages to physical pages in which logical page B is swapped with the gap. Logical page B is mapped to physical page 2 and the gap is mapped to physical page 1 (e.g. by updating a gap pointer). Mapping of other logical pages to physical pages remains as in FIG. 7C.

FIG. 7E illustrates a subsequent mapping of logical pages to physical pages in which logical page A is swapped with the gap. Logical page A is mapped to physical page 1 and the gap is mapped to physical page 0 (e.g. by updating a gap pointer). Mapping of other logical pages to physical pages remains as in FIG. 7D. Logical pages A-D have all been relocated by one position at this point (i.e. physical address incremented by 1).

FIG. 7F illustrates a subsequent mapping of logical pages to physical pages in which logical page D is swapped with the gap. Logical page D is mapped to physical page 0 and the gap is mapped to physical page 4 (e.g. by updating a gap pointer). Mapping of other logical pages to physical pages remains as in FIG. 7E. Thus, it can be seen that the gap has cycled around to physical page 4, where it started in FIG. 7A. During this gap cycle, each logical page was incremented by one physical page, e.g. logical page A, from 0 to 1, logical page B, from 1 to 2. The mapping of logical pages to physical pages is thus offset by one from the mapping shown in FIG. 7A with logical pages remaining in the same cyclic order. Any such mapping may be indicated very simply. For example, in addition to a gap pointer, a start pointer may indicate a start location (e.g. the location where logical page A is stored). Thus, the mapping of FIG. 7F could be indicated by a start pointer indicating physical page 1 and a gap pointer indicating physical page 4, while the mapping of FIG. 7C would be indicated by a start pointer indicating physical page 0 and a gap pointer indicating physical address 2.

FIG. 7G illustrates a mapping after a subsequent gap cycle (i.e. after a sequence of gap moves that brings the gap back to physical page 4). It can be seen that the logical pages are incremented by another physical page by this gap cycle (i.e. offset by two pages from the mapping of FIG. 7A). Thus, the start pointer would indicate physical page 2 and the gap pointer would indicate physical page 4 for this mapping.

FIG. 7H illustrates a mapping after a subsequent gap cycle. It can be seen that the logical pages are incremented by another physical page by this gap cycle (i.e. offset by three pages from the mapping of FIG. 7A). Thus, the start pointer would indicate physical page 3 and the gap pointer would indicate physical page 4 for this mapping.

FIG. 7I illustrates a mapping after a subsequent gap cycle. It can be seen that the logical pages are incremented by another physical page by this gap cycle (i.e. offset by four pages from the mapping of FIG. 7A). Thus, the start pointer would indicate physical page 0 and the gap pointer would indicate physical page 4 for this mapping. This represents the same mapping as in FIG. 7A so that a full cycle has been completed and the cycle begins again. The scheme illustrated in FIG. 7A-I provides a simple deterministic (mathematical) wear leveling scheme that does not require maintaining a full logical to physical map. A mapping can be indicated by just two pointers representing the start location and gap location and may be referred to as a “start gap” scheme. This represents a significantly lower overhead than recording large numbers of individual page mappings. Other deterministic mapping schemes may also be used to map logical addresses to physical addresses in a manner that changes the mapping in a predetermined manner (e.g. according to a mathematical scheme) that can be represented by a relatively small amount of data (significantly less than a full look-up index table). For example, U.S. Patent Publication Number 2017/0177470, “Access network for address mapping in non-volatile memories” describes examples that may provide alternative regional wear leveling schemes.

A mathematical wear leveling scheme may be applied across an entire non-volatile memory as a single unit. However, for large memories, this may not provide sufficient movement to avoid memory cell wear out. For example, for a 1TiB (one binary terabyte or one times 2{circumflex over ( )}40 bytes) memory with a physical page size of 64 B, it would take more than 17 billion (1.7E10) gap moves to complete a gap cycle. In other examples, memories may be accessed in different units of read (e.g. 128 B, 256 B, or other unit) and memories may be of any size. For some types of memory with relatively low endurance, this would allow a physical page to be worn out during a gap cycle (e.g. some Storage Class Memory (SCM) memories have estimated or targeted endurance of about 5E5 writes). In some cases, an individual logical address may be sequentially written many times (e.g. because of malicious attack) so that a physical page may be worn out before a gap would remap the logical page. For various medias and interfaces the behavior at the end of endurance when the device is worn out may vary. It is possible for the media to have a predicted endurance that will be over or under achieved in actual deployment. Further, it is possible for the device to have knowledge of the pre-existing media expectations. Thus, the end of endurance can be through some monitoring or behavior change, or it may be assumed by the controller pre-emptively.

FIG. 8 illustrates an example of a non-volatile memory 800 that is mapped into N regions, with each region independently applying a mathematical wear leveling scheme (e.g. a start gap scheme). Different instances of a start gap wear leveling scheme are applied separately in regions 1-N. The size of a region (number of regions for a given memory) and the frequency of gap movement may be selected according to different goals. Those goals may be to match expected media endurance capabilities against host workloads of concern. A specific example is to choose group size and gap movements that would disrupt a series of sequential writes to an individual logical address before reaching an endurance limit of a physical page, e.g. for expected endurance of about 5E5 writes, a gap cycle should take fewer than 5E5 writes, for example 1E5 writes. Control circuits (e.g. in a controller such as controller 112) are configured to map a set of non-volatile memory cells into a plurality of regions (e.g. according to firmware that specifies a mapping scheme). Inclusion of other mitigating factors may be included in any example prediction. Examples of these mitigating factors include different media programming or sensing voltages, device controller cache, device throughput throttling, reduced host workload support, or other device controller features.

FIGS. 9A-B illustrate a non-volatile memory 900 that is mapped into four regions with each of regions 1-4 operating a regional wear leveling scheme (an independent instance of a mathematical wear leveling scheme in this example). The mapping of logical pages to regions is fixed in this example, so that logical pages A-D are mapped to region 1, logical pages E-H are mapped to region 2, logical pages I-L are mapped to region 3, and logical pages M-P are mapped to region 4. Mapping of non-volatile memory cells into regions may be performed as part of initialization and may be performed by a memory controller that is configured to map non-volatile memory cells into regions. FIG. 9B is a table that indicates the mapping of logical addresses to regions. While such a scheme distributes wear within each individual region, some regions may receive more wear than others in such a scheme (e.g. logical pages A-D may be frequently written causing region 1 to wear out rapidly). Thus, one region may wear out prematurely and cause a memory system to fail while other regions have significant remaining life expectancy.

In some non-volatile memory, in addition to regional wear leveling schemes operating within regions, an inter-region wear leveling scheme may distribute wear between regions. Such inter-region wear leveling may avoid concentration of wear in any particular region so that early wear out of a region may be avoided.

FIGS. 10A-B illustrate a non-volatile memory 1000 that has an inter-region wear leveling scheme that operates between regions 1-5, in addition to individual regional wear leveling schemes operating within each region 1-5. FIG. 10A shows non-volatile memory cells of non-volatile memory 1000 mapped into regions 1-5 with data stored in regions 1-4, with each of regions 1-4 having a respective gap according to its wear leveling scheme. No data is stored in region 5. FIG. 10B is a table that indicates the mapping of groups of logical pages to regions for non-volatile memory 1000. It can be seen that region 5 is not mapped to any logical pages in this example but instead is a gap in the mapping scheme. An example of an inter-region wear leveling scheme operates by moving this gap from region to region in a similar manner to the start gap wear leveling scheme of FIGS. 7A-I. Thus, in addition to applying a first wear leveling scheme in a given region (e.g. region 1) a second wear leveling scheme is applied between regions 1-5 in this example.

FIG. 11A shows non-volatile memory 1000 after a first gap move from region 5 to region 4. Logical pages M-P are relocated from region 4 to region 5 and the gap is relocated from region 5 to region 4 as indicated by the table of FIG. 11B. Other logical page to region mapping remains as before. The updated mapping may be recorded by a pointer as before or in a table maintained by a memory system to record allocation of logical addresses to regions (e.g. as shown in FIG. 11B). While moving region 4 into region 5, it is possible to move one page at a time while tracking the progress of the move with a pointer. If accessing an Logical pages M-P, a comparison for above or below the pointer will determine if the data is still in region 4 or already transitioned to region 5. These transitions may be done one Logical page at a time, or it may be accomplished in groups of moves (i.e. two or more transitions at a time). In some cases, an entire region may be copied into cache prior to being written back to the non-volatile memory and no copy may remain in the non-volatile memory during this transition. The transitions between regions may be tracked with a pointer or other tracking scheme.

FIG. 12A shows non-volatile memory 1000 after a second gap move from region 4 to region 3. Logical pages I-L are relocated from region 3 to region 4 and the gap is relocated from region 4 to region 3 as indicated by the table of FIG. 12B. Other logical page to region mapping remains as before. The updated mapping may be recorded by a pointer as before or in a table maintained by a memory system to record allocation of logical addresses to regions (e.g. as shown in FIG. 12B).

FIG. 13A shows non-volatile memory 1000 after a third gap move from region 3 to region 2. Logical pages E-H are relocated from region 2 to region 3 and the gap is relocated from region 3 to region 2 as indicated by the table of FIG. 13B. Other logical page to region mapping remains as before. The updated mapping may be recorded by a pointer as before or in a table maintained by a memory system to record allocation of logical addresses to regions (e.g. as shown in FIG. 13B).

FIG. 14A shows non-volatile memory 1000 after a fourth gap move from region 2 to region 1. Logical pages A-D are relocated from region 1 to region 2 and the gap is relocated from region 2 to region 1 as indicated by the table of FIG. 14B. Other logical page to region mapping remains as before. The updated mapping may be recorded by a pointer as before or in a table maintained by a memory system to record allocation of logical addresses to regions (e.g. as shown in FIG. 14B). A subsequent gap move returns the gap to region 5 and so on, with the mapping of logical addresses incrementing by one region for each gap cycle. Though not explicitly shown in the above figures, it will be understood that each region may continue its regional wear leveling scheme between steps in the inter-region wear leveling scheme which are generally less frequent. While regional wear leveling operates at a page level, inter-region wear leveling operates over a larger unit of data of a group of logical pages and may require multiple copy operations. One or more pointers may be used to track such copying to allow resumption if copying is interrupted. While inter-region wear leveling may be performed at discrete intervals in some cases (e.g. during idle time when there is little or no impact on host operations or during a power-up or booting routine) in some cases, inter-region wear leveling is performed continuously with relocations interleaved with host access operations so that gap moves proceed while host access operations are performed (e.g. servers that may be in continuous operation and may not have idle time).

While the same type of wear leveling scheme (start gap wear leveling) is used for both regional wear leveling and inter-region wear leveling in this example, different wear leveling schemes may also be used and inter-regional wear leveling may operate substantially independently of regional wear leveling. Remapping in an inter-region wear leveling scheme may be performed in response to a triggering event such as an amount of elapsed time, or an amount of wear indicated by a threshold number of read and/or write and/or erase operations performed on the memory, or some other event. A count may be maintained for a memory such as non-volatile memory 1000 that indicates wear across regions (e.g. by summing individual write counts maintained for individual regions for respective regional wear leveling schemes, sampling across regions, or otherwise). The number of writes that triggers an inter-region remapping may be selected according to a number of factors including, for example, the disparity in wear between regions (e.g. as indicated by individual write counts), disparity of access intensity, estimated endurance of memory cells, region size, and/or other factors.

In some cases, host logical addresses may be grouped and assigned to regions by simply dividing a host logical address space into contiguous ranges with each range forming a group. In other cases, host addresses may be grouped according to data access patterns so that, for example, frequently written addresses are grouped together and infrequently written addresses are also grouped together. In other examples, frequently accessed and infrequently accessed data may be grouped together to produce groups of logical pages with similar overall wear for each group.

FIG. 15 shows an example in which received logical data from a host is divided into four groups 1-4 on the basis of expected access patterns (e.g. expected write frequency). A first group of logical pages A-D, Group 1, is expected to be written with low frequency. Groups 2 and 3, consisting of logical pages E-H and I-L respectively, are expected to be written with medium frequency. Group 4, consisting of logical pages M-P are expected to be written with high frequency. Information about host access patterns may be obtained from a host (e.g. via indicators of expected host access patterns associated with host logical addresses), heuristically extracted due device monitoring, cache effectiveness monitoring, or other indicators. In some cases, the access patterns may be used to group data accordingly, e.g. by grouping host logical addresses with similar access patterns together, or by mixing data with different access patterns. For example, a host that is in communication using the NVMe protocol may specify one or more NVMe namespaces that indicate host logical address ranges with specified characteristics including expected access frequency information. A group may be considered as a form of intermediate logical address or intermediate logical page (ILP).

In some memory arrays, some areas of the memory may have less desirable media properties than others. For example, in memories some layers may have lower endurance, retention, voltage disturbs, bit error rate accumulations, or media predictability than others. In one example, locations with lower or higher endurance may be known for a given memory design and may be common to all memories of a given design so that a prediction of endurance may be made prior to use. Endurance predictions may also be obtained from testing, or observed behavior (e.g. error rate found by ECC), and indications of endurance expectations may be recorded during testing for later use. Physical areas with similar media property expectations may be assigned to the same region so that memory cells within a given region have similar endurance expectations. Alternatively, the regions may be constructed of diverse media expectations to drive a more average and even behavior throughout the drive. The mapping of non-volatile memory cells into a plurality of regions (e.g. in physical pages or blocks) may be based on address order (e.g. contiguous physical addresses are mapped to different groups so that physical pages 0 to N−1 are in a first region, N to 2N−1 in a second region, and so on). Addresses may be scrambled or hashed before being assigned to regions, selected in a stepped order (e.g. counting mod x so that region 1 includes physical pages 1, 1+x, 1+2x, and so on), or otherwise selected according to sorting scheme. Layouts of the regions may be made to optimize for performance and expected access conflicts for target workloads (for example regions may be configured for any of: sequential accesses, 4 kB accesses for block storage to memory accesses, media die access conflicts (i.e. configured to avoid subarray, plane, die, or partition access conflicts by distributing potentially-conflicting data across subarrays, planes, dies, or partitions)). A region may be considered an intermediate physical address or intermediate physical block (IPB) with each region having capacity to store one group to allow groups to be mapped to regions in a one-to-one mapping.

FIG. 16 shows an example of a memory in which non-volatile memory cells are mapped into 5 regions that are classified according to their expected endurance. Regions 1 and 5 are classified as low endurance regions. Region 2 is classified as a high endurance region. Regions 3 and 4 are classified as medium endurance regions. Each region may be formed of physical areas that are expected to have similar endurance characteristics (similar expected endurance limits) and may be physically dispersed across multiple devices. Mapping of non-volatile memory cells into regions may be performed in any suitable sized unit (e.g. by page, block, or other unit) and may be a static mapping or may be dynamic, i.e. some remapping may occur during operation. Mapping of a set of non-volatile memory cells into a plurality of regions may be performed by a memory controller (e.g. according to firmware) and may be performed as part of an initialization and/or subsequent to initialization.

Knowing likely data access patterns and/or endurance expectations for different regions allows such factors to be taken into account when assigning logical data to regions. For example, data that is frequently accessed may be assigned to regions that have high endurance while infrequently accessed data may be assigned to regions that have low endurance. Alternatively, two regions of high access rate may be placed for minimal access conflicts. Access operations include read and write operations, and may include erase operations in memories that perform erase between writes. Write operations are generally associated with wear and a write count may be used as a measure of wear. In some cases, read operations may also cause wear and may be considered when measuring wear (e.g. in addition to write operations in a weighted scheme). While examples described refer to write operations as examples of memory access operations, it will be understood that other memory access operations such as read, erase, refresh or other operations may also be considered when estimating wear.

FIGS. 17A-B illustrate a mapping of logical pages of FIG. 15 to regions of FIG. 16 according to access frequency and endurance. Logical pages A-D, which have low expected access frequency, are mapped to region 1, which has low endurance. Logical pages M-P, which have high expected access frequency, are mapped to region 2, which has high endurance. Logical pages E-H and I-L, which have medium expected access frequency are mapped to region 4, which has medium endurance. A gap for an inter-region wear leveling scheme is assigned to region 5, which has low endurance. This may represent an initial mapping in a memory so that at least initially data is assigned in a manner that accounts for different expected access patterns and different endurance characteristics. While regions are classified into just three classes (low, medium, and high endurance) in this example, it will be understood that any number of classes may be used. Similarly, host access frequency may be divided into any suitable number of classes. Subsequent to the mapping shown in FIGS. 17A-B an inter-region wear leveling scheme may be applied so that the mapping shown is changed. While an inter-region wear leveling scheme may be a mathematical wear leveling scheme that blindly remaps logical groups between physical regions, in some cases an inter-region wear leveling scheme may be based on actual or estimated wear.

FIG. 18 shows an example of data that is remapped from a first mapping to a second mapping according to an indicator of wear shown in the right column. The indicator may be a total number of writes experienced by the region, number of gap cycles (which is a fraction of the total number of writes), number of full cycles (which is a smaller fraction of the total number of writes), a statistically estimated number of writes based on sampling, or some other metric. It can be seen that region 3, containing logical pages I-L has an indicator that indicates higher wear than any other region. Therefore, the group containing logical pages I-L is relocated to region 5 (which has been unused up to this point) so that the most frequently written data is relocated to the least worn region. An indicator of wear may be maintained for each region and/or for each logical group of data. Such a scheme may be based on observed wear per region and may be implemented with or without indicators of access frequency information from a host, and with or without information about expected endurance for different regions. A map may be maintained to identify which logical group of pages is mapped to which region. The number of regions is generally a small fraction of the number of pages so that such a map represents a relatively small overhead. Mathematical wear leveling may be used for regional wear leveling so that such a system benefits from the simplicity of mathematical wear leveling at a regional level and also benefits from the adaptability of wear leveling based on recorded wear data at the inter-regional level. Thus, two levels of wear leveling (regional and inter-region) are provided in this example. In other examples, three or more layers of wear leveling may be provided (e.g. another layer above the one illustrated in FIG. 18, with regions 1-5 forming a single region in a higher-level scheme). At any level, wear leveling may be mathematical or may be based on media properties such as expected endurance or other properties.

FIG. 19 shows an example of a non-volatile memory system 1900 that maintains indicators of wear for each region in a first table 1902 and maintains a recording of access frequency for each group of logical pages in a second table 1904. It will be understood that during an initial mapping period, these numbers will be equal (i.e. the number of writes experienced by a region will be equal to the number of writes to the group of logical pages assigned to the region). However, as groups are moved to distribute wear during a period of use, these numbers diverge. While groups of logical data may have widely different numbers of writes, regions tend to have numbers of writes that are in a narrower range due to wear leveling. Tables such as tables 1902 and 1904 allow groups of logical pages to be remapped to physical regions according to wear, for example, to evenly distribute wear, or to distribute wear according to expected media properties of different regions including their estimated endurance. While the above examples refer to estimated endurance as an example of a media property that may be used in implementations of the present technology, other media properties may also be used, either alone or in combination, including bit error accumulation rate, retention, sensitivity to disturbs and other media properties that may indicate a deterioration in physical memory. Furthermore, while access rate, or number of writes, is used as an access parameter in examples above, it will be understood that other memory access parameters may also be used in a wear leveling scheme, including time since last access, burst access versus steady access, localized versus dispersed access, access size, and other factors.

FIG. 20 illustrates an example of a method that includes applying a first instance of a regional wear leveling scheme in a first region of a non-volatile memory 2002, applying a second instance of the regional wear leveling scheme in a second region of the non-volatile memory 2004; and applying an inter-region wear leveling scheme between the first region of the non-volatile memory and the second region of the non-volatile memory 2006. It will be understood that the number of regions in this example is two for simplicity but that some memory systems may have much larger numbers of regions.

The regional wear leveling scheme may be a mathematical wear leveling scheme that includes rotating a mapping of logical addresses to physical addresses in a predetermined cyclical pattern (e.g. by incrementing an offset as previously shown in FIGS. 7A-I). Inter-regional wear leveling may also be mathematical wear leveling, e.g. may include rotating the mapping of groups of logical addresses to regions according to a predetermined cyclical pattern. Alternatively, wear indicators may be maintained for the first and second regions (and any other regions) and the inter-region wear leveling scheme may remap groups of data between regions according to such wear indicators. Indicators of expected access patterns may be used to initially group data, e.g. keeping data with similar host access patterns together so that frequently written data is in one or more groups and infrequently written data is in other groups. In some cases, indicators of expected host access patterns associated with host logical addresses may be sent by a host and host logical addresses may be grouped according to the one or more indicators of expected host access patterns into at least a first group assigned to a first region of the non-volatile memory and a second group assigned to a second region of the non-volatile memory (e.g. grouped into frequently written and infrequently written groups that are written to different regions). In some cases, host data access patterns may be identified from a plurality of host access commands and host logical addresses may be grouped according to the host data access patterns into at least a first group assigned to the first region of the non-volatile memory and a second group assigned to the second region of the non-volatile memory (e.g. grouped into frequently written and infrequently written groups that are written to different regions).

FIG. 21 illustrates an example embodiment of regional and inter-region wear leveling that may be implemented in a non-volatile memory system such as non-volatile memory system 100 (e.g. in media management layer 238). A command queue 2102 contains commands received from a host including commands with host logical addresses (LAs) from 0 to N. Group sorting module 2104 sorts logical addresses according to group, where host logical addresses have been previously assigned to groups (e.g. groups of equal size that contain data for one region of non-volatile memory, in other examples groups may be of unequal size) and groups have been assigned to regions. FIG. 21 illustrates a regional wear leveling module 2106 that applies a regional wear leveling scheme for a corresponding region that stores a group comprised of M host logical addresses that are assigned to local logical addresses 0-M (other host logical address ranges may be similarly assigned to local logical addresses 0-M for other regional wear leveling modules so LAA=0 in a given region does not mean LA=0). Other regional wear leveling modules apply a wear leveling scheme in other regions in a similar manner. Group sorting module 2104 identifies other host logical address ranges that correspond to one or more other groups 2108 that implement other instances of a regional wear leveling scheme in parallel. A group command queue 2110 contains only commands for the group or region (similar components are present in other regions for handling respective commands). A command passes from group command queue 2110 to location decoder 2112, which identifies a physical address corresponding to the command. Location decoder 2112 may maintain pointers, for example, start and gap pointers as previously described, to enable a simple decoding of logical addresses without requiring a map of all logical addresses. A count update output is provided to a wear leveling movement module 2114 as required. For example, a count update may be sent for every write command. Wear leveling movement module 2114 maintains a count of write commands and implements movement of data in response to a triggering event, for example after a predetermined number of write commands. Implementation in this example includes generating movement commands that are sent to the group command queue for subsequent execution (e.g. copying of data to a gap from a neighboring line) and generating updates to any pointers used by location decoder 2112 (e.g. updating a gap pointer and/or updating a start pointer). Location decoder 2112 generates an abstract physical address (APA) in the range 0-P (e.g. by incrementing a local logical address), which is converted into a physical address (PA) by physical mapping module 2116 (e.g. into an address that specifies a physical location in terms of a die, bank, subarray, or other physical unit). These commands are placed in a physical command queue 2118 and from there pass to a scheduler 2120 to be executed in the non-volatile memory array. In this example, the number of abstract physical addresses in a region, P, is greater than the number of local logical addresses M, e.g. P=M+1, to allow for a gap. In other regional wear leveling schemes this may not be the case, e.g. in some cases M=P.

The regional wear leveling scheme of FIG. 21 may be implemented independently in each region and is not visible to a host. Regional wear leveling module 2106 may be considered a means for operating an instance of a mathematical wear leveling scheme in a region of non-volatile memory while other similar modules act as means for operating other instances of the mathematical wear leveling scheme in other regions of the non-volatile memory. Inter-region wear leveling may be implemented by changing logical address ranges mapped to regions, e.g. by reconfiguring group sorting module 2104 and copying data between regions. Thus, group sorting module 2104 may be considered a means for operating an inter-region wear leveling scheme between at least the first region and the second region. Thus, while regional wear leveling module 2106 applies a first wear leveling scheme in a first region of the plurality of regions, group sorting module 2104 applies a second wear leveling scheme between the plurality of regions.

The components of FIG. 21 may be physically located together (e.g. in a single memory controller) or may be located separately. For example, Group sorting module 2104 may be in a memory controller (e.g. in a media management module) while regional wear leveling module 2106 may be physically separate, e.g. in a lower level controller in a memory die, bank, subarray, or other unit of memory. In some cases, a regional wear leveling module may communicate with an inter-regional wear leveling module such as group sorting module 2104 to coordinate regional and inter-regional wear leveling. In other cases, regional and inter-regional wear leveling may be independent. Their implementations may be split across different aspects of the controller. For example, the group sorting may be in hardware, but the group movement may be FW managed or initiated.

An example of a non-volatile storage apparatus includes: a set of non-volatile memory cells; and one or more control circuits in communication with the set of non-volatile memory cells, the one or more control circuits are configured to map the set of non-volatile memory cells into a plurality of regions, apply a first wear leveling scheme in a first region of the plurality of regions, and apply a second wear leveling scheme between the plurality of regions.

The first wear leveling scheme may be a deterministic wear leveling scheme. The set of non-volatile memory cells may have an expected endurance limit and the first wear leveling scheme may be configured to remap received logical data at a rate sufficient to ensure remapping of a sequence of writes to an individual logical address from a first physical address to a second physical address before the expected endurance limit of the first physical address is reached. The one or more control circuits may be configured to record wear data for the plurality of regions and the second wear leveling scheme may be based on the wear data for the plurality of regions. The one or more control circuits may be configured to obtain access frequency information for logical address ranges used by a host, and the second wear leveling scheme may be further based on the access frequency information. The one or more control circuits may be configured to obtain the access frequency information through indicators of access frequency sent by the host. The one or more control circuits may be configured to obtain the access frequency information through recording of access frequency experienced over a period of use. The set of non-volatile memory cells may comprise phase change memory cells. The set of non-volatile memory cells may comprise Resistive Random Access Memory (ReRAM) cells, PCM, NAND, NOR, MRAM, etc. The set of non-volatile memory cells may be formed in a plurality of memory levels disposed above a substrate in a monolithic three-dimensional memory structure. The one or more control circuits may be configured to individually apply the first wear leveling scheme to each of the plurality of regions, the first wear leveling scheme is a start gap scheme, region size and rate of remapping of the start gap scheme may be sufficient to remap a series of sequential writes to an address prior to reaching an endurance limit, and wherein the second wear leveling scheme is based on recorded wear data for the plurality of regions.

An example of a method includes applying a first instance of a regional wear leveling scheme in a first region of a non-volatile memory; applying a second instance of the regional wear leveling scheme in a second region of the non-volatile memory; and applying an inter-region wear leveling scheme between the first region of the non-volatile memory and the second region of the non-volatile memory.

Applying the first instance of the regional wear leveling scheme in the first region may include rotating a mapping of logical addresses to physical addresses of the first region according to a predetermined cyclical pattern. Applying the inter-region wear leveling scheme may include rotating a mapping of groups of logical addresses to regions of the non-volatile memory according to a predetermined cyclical pattern. Applying the inter-region wear leveling scheme may include maintaining a first indicator of wear associated with the first region and a second indicator of wear associated with the second region and remapping data according to at least one of the first indicator of wear and the second indicator of wear. The method may further include: receiving, from a host, one or more indicators of expected host access patterns associated with host logical addresses and grouping host logical addresses according to the one or more indicators of expected host access patterns into at least a first group assigned to the first region of the non-volatile memory and a second group assigned to the second region of the non-volatile memory. The method may further include identifying host data access patterns from a plurality of host access commands and grouping host logical addresses according to the host data access patterns into at least a first group assigned to the first region of the non-volatile memory and a second group assigned to the second region of the non-volatile memory.

An example of a system includes: a first region of non-volatile memory; a second region of non-volatile memory; means for operating a first instance of a mathematical wear leveling scheme in the first region of non-volatile memory; means for operating a second instance of the mathematical wear leveling scheme in the second region of non-volatile memory; and means for operating an inter-region wear leveling scheme between at least the first region of non-volatile memory and the second region of non-volatile memory.

The system may further include means for maintaining a first indicator of wear for the first region of non-volatile memory and a second indicator of wear for the second region of non-volatile memory. The system may further include: means for receiving, from a host, an expected data access pattern; and means for grouping host logical addresses according to the expected data access pattern.

For purposes of this document, reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “another embodiment” may be used to describe different embodiments or the same embodiment.

For purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via intervening elements. When an element is referred to as being directly connected to another element, then there are no intervening elements between the element and the other element. Two devices are “in communication” if they are directly or indirectly connected so that they can communicate electronic signals between them.

For purposes of this document, the term “based on” may be read as “based at least in part on.”

For purposes of this document, without additional context, use of numerical terms such as a “first” object, a “second” object, and a “third” object may not imply an ordering of objects but may instead be used for identification purposes to identify different objects.

For purposes of this document, the term “set” of objects may refer to a “set” of one or more of the objects.

The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the proposed technology and its practical application, to thereby enable others skilled in the art to best utilize it in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto. 

What is claimed is:
 1. A non-volatile storage apparatus, comprising: a set of non-volatile memory cells; and one or more control circuits in communication with the set of non-volatile memory cells, the one or more control circuits are configured to map the set of non-volatile memory cells into a plurality of regions, group logical address ranges used by a host into a plurality of groups according to expected access frequency information, assign the plurality of groups to the plurality of regions according to the expected access frequency information, apply a first wear leveling scheme in each of the plurality of regions, remapping according to the first wear leveling scheme triggered by a first number of writes in a first region, the first number selected according to expected endurance characteristics of the first region and remapping according to the first wear leveling scheme triggered by a second number of writes in a second region, the second number selected according to expected endurance characteristics of the second region and apply a second wear leveling scheme between the plurality of regions, the second wear leveling scheme is based on the expected access frequency information, the expected access frequency information is obtained through indicators of expected access frequency sent by the host.
 2. The non-volatile storage apparatus of claim 1 wherein the first wear leveling scheme is a deterministic wear leveling scheme.
 3. The non-volatile storage apparatus of claim 2 wherein the set of non-volatile memory cells have an expected endurance limit and the first wear leveling scheme is configured to remap received logical data at a rate sufficient to ensure remapping of a sequence of writes to an individual logical address from a first physical address to a second physical address before the expected endurance limit of the first physical address is reached.
 4. The non-volatile storage apparatus of claim 1 wherein the one or more control circuits are configured to record wear data for the plurality of regions and the second wear leveling scheme is based on the wear data for the plurality of regions.
 5. The non-volatile storage apparatus of claim 4 wherein the second wear leveling scheme assigns logical addresses with low expected access frequency to regions with high wear and assigns logical addresses with high expected access frequency to regions with low wear.
 6. The non-volatile storage apparatus of claim 1 wherein the indicators of access frequency sent by the host specify expected access frequency information for one or more NVMe namespaces.
 7. The non-volatile storage apparatus of claim 1 wherein the one or more control circuits are configured to obtain additional access frequency information through recording of access frequency experienced over a period of use.
 8. The non-volatile storage apparatus of claim 1 wherein the set of non-volatile memory cells comprise phase change memory cells.
 9. The non-volatile storage apparatus of claim 1 wherein the set of non-volatile memory cells comprise Resistive Random Access Memory (ReRAM) cells.
 10. The non-volatile storage apparatus of claim 1 wherein the set of non-volatile memory cells are formed in a plurality of physical memory levels disposed at different heights above a substrate in a monolithic three-dimensional memory structure, the first region is formed at a first physical memory level, the second region is firmed at a second physical memory level, and the expected endurance characteristics of the first and second regions are obtained from respective heights above the substrate of the first and second physical memory levels.
 11. The non-volatile storage apparatus of claim 1 wherein the one or more control circuits are configured to individually apply the first wear leveling scheme to each of the plurality of regions, the first wear leveling scheme is a start gap scheme, region size and rate of remapping of the start gap scheme are sufficient to remap a series of writes to an address prior to reaching an endurance limit, and wherein the second wear leveling scheme is based on recorded wear data for the plurality of regions.
 12. A method, comprising: receiving, from a host, one or more indicators of expected host access patterns associated with host logical addresses; grouping host logical addresses according to the one or more indicators of expected host access patterns into at least a first group and a second group; determining expected endurance characteristics of at least a first region of a non-volatile memory located at a first physical level above a substrate and a second region of the non-volatile memory located at a second physical level above the substrate, expected endurance characteristics of the first and second regions determined from the first and second physical levels above the substrate; initially assigning the first group to the first region of the non-volatile memory and the second group to the second region of the non-volatile memory such that a group with higher expected access frequency is assigned to a region with higher expected endurance; applying a first instance of a regional wear leveling scheme in the first region of the non-volatile memory in an initial period; applying a second instance of the regional wear leveling scheme in the second region of the non-volatile memory in the initial period; and subsequently applying an inter-region wear leveling scheme between the first region of the non-volatile memory and the second region of the non-volatile memory according to recorded access frequency that is recorded in the initial period.
 13. The method of claim 12 wherein applying the first instance of the regional wear leveling scheme in the first region includes rotating a mapping of logical addresses to physical addresses of the first region according to a predetermined cyclical pattern.
 14. The method of claim 12 wherein applying the inter-region wear leveling scheme includes rotating a mapping of groups of logical addresses to regions of the non-volatile memory according to a predetermined cyclical pattern.
 15. The method of claim 12 wherein applying the inter-region wear leveling scheme includes maintaining a first indicator of wear associated with the first region and a second indicator of wear associated with the second region and remapping data according to at least one of the first indicator of wear and the second indicator of wear.
 16. The method of claim 12 wherein applying the first instance of the regional wear leveling scheme in the first region includes remapping in response to a first write count in the first region, the first write count selected according to the expected endurance characteristics of the first region and applying the second instance of the regional wear leveling scheme in the second region includes remapping in response to a second write count in the second region, the second write count selected according to the expected endurance characteristics of the second region.
 17. The method of claim 12 further comprising: identifying host data access patterns from a plurality of host access commands.
 18. A system comprising: a first region of non-volatile memory located at a first height above a substrate, the first region having high expected endurance based on the first height; a second region of non-volatile memory located at a second height above the substrate, the second region having low expected endurance; means for operating a first instance of a mathematical wear leveling scheme in the first region of non-volatile memory, remapping according to the first instance of the mathematical wear leveling scheme triggered by a first number of writes in the first region, the first number selected according to the high expected endurance; means for operating a second instance of the mathematical wear leveling scheme in the second region of non-volatile memory, remapping according to the second instance of the mathematical wear leveling scheme triggered by a second number of writes in the second region, the second number selected according to the low expected endurance of the second region; means for operating an inter-region wear leveling scheme between at least the first region of non-volatile memory and the second region of non-volatile memory; means for receiving, from a host, a plurality of indicators of expected write frequency; and means for grouping host logical addresses according to the plurality of indicators of expected write frequency into a first group having high expected write frequency and a second group having low expected write frequency, initially assigning the first group to the first region, and assigning the second group to the second region according to expected endurance characteristics of the first region and the second region.
 19. The system of claim 18 further comprising means for maintaining a first indicator of wear for the first region of non-volatile memory and a second indicator of wear for the second region of non-volatile memory.
 20. The system of claim 18 wherein the set of non-volatile memory cells comprise Resistive Random Access Memory (ReRAM) cells. 